stm32 pwm 占空比可变函数-皇冠最新app版本

频率 10k，占空比可以达到1%变化的精度，100k只能是10%的变化精度。

#define pwm_clk1m_arr_10k 100-1

void izadcpwminit(uint8_t duty)//10%~90%

{

  if(duty>90)

  {

 duty = 90;

  }

  if(duty<10)

  {

 duty = 10;

  } 

//reset 

  /* tim4 enable counter */

  tim_cmd(tim4, disable);

   /* tim4 main output enable */

  tim_ctrlpwmoutputs(tim4, disable); 

//end of reset

    /* system clocks configuration */

  rccpwmadcconfiguration();

  /* gpio configuration */

  gpiopwmadcconfiguration();

  /* -----------------------------------------------------------------------

    tim3 configuration: generate 4 pwm signals with 4 different duty cycles:

    the tim3clk frequency is set to systemcoreclock (hz), to get tim3 counter

    clock at 24 mhz the prescaler is computed as following:

     - prescaler = (tim3clk / tim3 counter clock) - 1

    systemcoreclock is set to 72 mhz for low-density, medium-density, high-density

    and connectivity line devices and to 24 mhz for low-density value line and

    medium-density value line devices

    the tim3 is running at 36 khz: tim3 frequency = tim3 counter clock/(arr 1)

                                                  = 24 mhz / 666 = 36 khz

    tim3 channel1 duty cycle = (tim3_ccr1/ tim3_arr)* 100 = 50%

    tim3 channel2 duty cycle = (tim3_ccr2/ tim3_arr)* 100 = 37.5%

    tim3 channel3 duty cycle = (tim3_ccr3/ tim3_arr)* 100 = 25%

    tim3 channel4 duty cycle = (tim3_ccr4/ tim3_arr)* 100 = 12.5%

  ----------------------------------------------------------------------- */

  /* compute the prescaler value */

  //prescalervalue = (uint16_t) (systemcoreclock / 24000000) - 1;//24m

  //tim3 frequency=1mhz/(9999 1) =100hz

  prescalervalue = (uint16_t) (systemcoreclock / 1000000) - 1; //tim3 counter clock: 1mhz

  /* time base configuration */

  //tim_timebasestructure.tim_period = 665;//(arr)

  //tim3 frequency=1mhz/(9999 1) =100hz

  //tim_timebasestructure.tim_period = 10000-1;  //tim3 counter clock/tim3 frequency

  //tim3 frequency=1mhz/(99 1) =10 000hz

  tim_timebasestructure.tim_period = pwm_clk1m_arr_10k;//pwm_clk1m_arr_100;  //tim3 counter clock/tim3 frequency 

  tim_timebasestructure.tim_prescaler = prescalervalue;

  tim_timebasestructure.tim_clockdivision = 0;

  tim_timebasestructure.tim_countermode = tim_countermode_up;

  tim_timebaseinit(tim4, &tim_timebasestructure);

  /* pwm1 mode configuration: channel1 */

  tim_ocinitstructure.tim_ocmode = tim_ocmode_pwm1;

  tim_ocinitstructure.tim_outputstate = tim_outputstate_enable;

  //ccr1_val =tim3_arr*duty/100;

 // tim_ocinitstructure.tim_pulse = ccr1_val;

 // tim_ocinitstructure.tim_pulse = (uint16_t)(10000-1)*duty/100; 

  tim_ocinitstructure.tim_pulse = (uint16_t)(pwm_clk1m_arr_10k)*duty/100;   

  tim_ocinitstructure.tim_ocpolarity = tim_ocpolarity_high;

//  tim_oc1init(tim3, &tim_ocinitstructure);

//  tim_oc1preloadconfig(tim3, tim_ocpreload_enable);

//pb6: tm4 channel1  

  tim_oc1init(tim4, &tim_ocinitstructure);

  tim_oc1preloadconfig(tim4, tim_ocpreload_enable); 

//pb8: tm4 channel3

  /* pwm1 mode configuration: channel3 */

  tim_ocinitstructure.tim_outputstate = tim_outputstate_enable;

  tim_ocinitstructure.tim_pulse = (uint16_t)(pwm_clk1m_arr_10k)*duty/100;   

  tim_oc3init(tim4, &tim_ocinitstructure);

  tim_oc3preloadconfig(tim4, tim_ocpreload_enable);

//pb7: tm4 channel2

  /* pwm1 mode configuration: channel2 */

  tim_ocinitstructure.tim_outputstate = tim_outputstate_enable;

  tim_ocinitstructure.tim_pulse =  (uint16_t)(pwm_clk1m_arr_10k)*duty/100; ;

  tim_oc2init(tim4, &tim_ocinitstructure);

  tim_oc2preloadconfig(tim4, tim_ocpreload_enable);

#if 0

  /* pwm1 mode configuration: channel4 */

  tim_ocinitstructure.tim_outputstate = tim_outputstate_enable;

  tim_ocinitstructure.tim_pulse = ccr4_val;

  tim_oc4init(tim3, &tim_ocinitstructure);

  tim_oc4preloadconfig(tim3, tim_ocpreload_enable);

#endif

  tim_arrpreloadconfig(tim4, enable);

  /* tim4 enable counter */

  tim_cmd(tim4, enable);

   /* tim4 main output enable */

  tim_ctrlpwmoutputs(tim4, enable);

}